1. Field of the Invention
The present invention relates to semiconductors and, more particularly, to an improved process for making complementary metal oxide semiconductor (CMOS) compatible bipolar CMOS (BiCMOS) devices.
2. Discussion of Related Art
A BiCMOS circuit includes both bipolar and complementary metal oxide semiconductor (CMOS) transistors in the same circuit. BiCMOS circuits enjoy advantages of both bipolar circuits and CMOS circuits. Bipolar circuits may drive high capacitive loads and thus provide large circuit fan outs and operate at high speed. CMOS circuits are relatively small in size and consume less power than other technologies. A typical BiCMOS device uses the bipolar circuits as a push-pull current booster and the CMOS circuits as logic circuits and to drive the base current of the bipolar circuits.
FIG. 1 is a schematic diagram of an example of a BiCMOS logic circuit 50 operating as an inverter. A totem pole-type output buffer 52 comprises a pull-up NPN bipolar transistor Q1 and a pull-down NPN bipolar transistor Q2. The base of transistor Q2 is coupled to an output terminal of a CMOS inverter 54 comprising a PMOS FET Q3 and an NMOS FET Q4. PMOS FET Q3 supplies a base current to bipolar transistor Q1 so that the logic circuit outputs a high voltage (data xe2x80x9c1xe2x80x9d). NMOS FET Q4 pulls a base charge from bipolar transistor Q1 so that the logic circuit outputs a low voltage (data xe2x80x9c0xe2x80x9d). The base of pull-down NPN bipolar transistor Q2 is connected to the source of NMOS FET Q5, which is turned on or off by the potential at the node of bipolar transistors Q1, Q2.
Many BiCMOS fabrication techniques are complicated and cannot be fabricated in standard CMOS foundries. This makes BiCMOS designs difficult to implement for integrated circuit designers that rely on standard CMOS foundries.
FIG. 2 is a cross-sectional view of a triple well polysilicon emitter BiCMOS device 200, which may be fabricated in a standard CMOS foundry. This device includes a p-type substrate 202 on which an NPN bipolar transistor 204 and CMOS device 206 are formed. The CMOS device comprises an NMOS device 208 and a PMOS device 210. The NPN transistor 204 includes a collector defined in an n-type c-well 212, a p-type base region 214, and an n+ emitter 216 formed by doped polysilicon. The NPN transistor 204 also includes an n+ n-plug collector ring 218 which contacts the collector 212 and reduces series resistance.
The NMOS device 208 is formed in a p-well 220 defined in the p-type substrate 202 and includes n+ drain and source regions 222A, 222B, and a gate oxide layer 224 on which a doped polysilicon p-type gate 226 is formed.
The PMOS device 210 is formed in an n-well 230 and includes p+ drain and source regions 232A, 232B, and a gate oxide layer 234 on which a doped polysilicon n-type gate 236 is formed. A number of field oxide regions 240 are defined on the surface as isolation areas between devices.
A prior art method for manufacturing this BiCMOS device 200 is illustrated with reference to FIGS. 3A-3H. FIG. 3A shows a p-type substrate 202. The substrate may be a conventional p-type wafer having a resistivity of about 6 to 9 xcexa9cmxe2x88x922. A 310 nm thick sacrificial oxide layer 302 is formed on the substrate to provide a protective layer for formation of the n-plug.
The sacrificial oxide layer 302 is etched from the areas where the n-plug ring collector 218 is to be formed. A second etch, removing 120 nm silicon for the c-well lithography alignment, is also performed. The photoresist layer is stripped and the wafer is cleaned. The wafer is exposed to an oxidation step to grow a 20 nm thick screen oxide for the following implant steps. The n-plug ring is formed by an implant of arsenic at an energy of 150 keV and a dose of 1xc3x971015 cmxe2x88x923. The result of these steps is illustrated in FIG. 3B.
Next, all of the oxide is stripped off of the wafer. A 30 nm stress release oxide (SRO) layer 304 is grown and then a 150 nm nitride layer 306 is deposited on the SRO layer by using low pressure chemical vapor deposition (LPCVD). These two layers are masked and the SRO and nitride layers 304, 306 are etched to create windows for forming the c-well 212. (These layers are also etched to create a window for the n-well 230 in the following step with the n-well mask.) When the windows are provided, the c-well implant is performed using a conventional implant of phosphorus at an energy of 150 keV with a maximum dose of 3xc3x971013 cmxe2x88x923. After the c-well and n-well implant, an n-well/c-well oxidation step is carried out at 1050xc2x0 C. to grow an oxide layer 307 of 4000 xc3x85. The result of these steps is shown in FIG. 3D.
Conventional CMOS steps follow: the nitride layer over the p-well is etched off and the p-well implant is carried out as the 3800 xc3x85 n-well/c-well oxide protects the n-well/c-well from the implant. The oxide layer 307 is then removed. A CMOS p-well drive-in step is carried out at 1150xc2x0 for 8 hours.
As seen in FIG. 3E, a number of field oxide regions (FOX) 240 are formed on the substrate 202. These FOX regions 240 may be formed in any well-known manner.
A gate oxide 234 is grown on the substrate surface in a conventional manner. Then, the gate oxide is etched off over the base area 214 to form a base window with a base mask. The result of these steps is shown in FIG. 3F.
Next, a base implant is performed using a p-type impurity such as BF2 at an energy of 80 keV and a typical dose of 2xc3x971013 cmxe2x88x923. This forms the p-type base 214. The wafer is cleaned and approximately 20 xc3x85 of oxide is removed using a precise oxide HF in 50:1 HF for 10 sec to remove oxide from the base area before polysilicon deposition. The result of these steps is shown in FIG. 3G.
Next, polysilicon deposition is performed. The NMOS and PMOS polysilicon gate structures 226, 236 are located on the gate oxide; a polysilicon emitter 217 is located on the substrate surface, in contact with the p-type base 214. The polysilicon emitter 217 is doped with an extremely high arsenic implant. The dose is as high as 1xc3x971016 cmxe2x88x923 at an energy of 50 keV, which is four times higher than a conventional CMOS polysilicon implant. This high dose eliminates the two dimensional effect for the narrow emitter and provides high emitter concentration for high emitter injection. A shallow emitter drive-in step is performed. This drive-in results in a very shallow n+ layer 216 in the base area 214.
The next step is the polysilicon patterning with over-etch to remove polysilicon stringers along steps as well as etching away the n+ layer 216 in the extrinsic base region formed during the emitter drive-in step. A normal CMOS over-etch process is used because of the gate oxide beneath the polysilicon to protect the source and drain regions. But in this case, the bipolar base part 214 is directly exposed to etching without oxide protection, so that a certain amount of silicon in the extrinsic base area is etched away. The result of these steps is shown in FIG. 3H.
Conventional CMOS steps follow including n-LDD, p-LDD, spacer formation, NMOS source and drain implant, and PMOS source and drain implant.
As noted above, this BiCMOS device may be fabricated in many CMOS foundries without substantially changing the CMOS components. The c-well has a uniform profile. That is, the c-well has a dopant concentration which is highest near the substrate surface and which decreases as it deepens from the surface. The c-well is doped in this manner to improve frequency-current response by lowering the c-well sheet resistance (Rsc). However, lowering Rsc degrades the BVceo i.e., collector-emitter breakdown voltage breakdown. Thus, in this device, the optimum Rsc which may be achieved is 300 xcexa9/sq and, as a tradeoff, a 4V BVceo and a maximum fT (cut off frequency) of 15 GHz. This is because a lower Rsc results in a higher fT.
It is an object of the present invention to provide a CMOS compatible BiCMOS fabrication technique which increases fT and maintains an acceptable BVceo.
This and other objects of the present invention are provided by a BiCMOS device having a c-well fabricated using profile engineering (a multi-energy implant using accurate dosages and energies determined by simulation) to provide a higher c-well implant dose while creating a narrow region with relatively low concentration in the collector depletion range to avoid low base-collector breakdown. This achieves a much lower collector series resistance to pull-up a frequency response, a collector sheet resistance which can be as low as 150 xcexa9/sq., fT may be increased to 20 GHz or higher, and epitaxial wafers are avoided. This latter advantage is desirable because epitaxial wafers are incompatible with CMOS processes performed by most foundries.
The c-well may be formed using profile engineering so that the carrier concentration near the base-collector junction in the collector region is made lower than the dopant concentration in the deep region of the c-well. For example, the base-collector junction may be formed with a depth of 0.25 xcexcm and have a regional (engineered) c-well carrier concentration less than 1017 cmxe2x88x923; and the c-well may have a doping concentration higher than 1017 cmxe2x88x923 at depths deeper than 0.6 xcexcm.
Also, a method according to a preferred embodiment of the present invention eliminates a silicon etch step during the collector ring formation procedures to provide a more efficient method for creating a BiCMOS device than previously possible.